In recent years, multiple functions are being implemented in system LSIs; from the standpoint of system cost reduction, architecture such as unified memory, such as DRAM, are often used. It has also become common for diverse DRAM access requests to be made to a single DRAM.
In addition, since system LSIs implemented with multiple functions, such as media processing, demand a high bandwidth, speed enhancement in DRAM is becoming increasingly necessary. Accordingly, memory manufacturers are competing fiercely in DRAM speed enhancement.
However, since the operation frequency of a DRAM memory cell itself has not changed from before, the minimum access size to DRAM is rapidly increasing from the perspective of system LSI. As a result, there are no problems transferring long data that is equivalent to a burst length, however there is the problem that when transmitting short data, the transference load of unnecessary data increases and the effective bandwidth will decrease. For example, there is the problem that, for media processing, the effective bandwidth for a motion compensation process necessary for video decoding will drop; this problem has conventionally been avoided by utilizing high cost DRAM, which tolerates this drop in effective bandwidth.
For increasing the effective bandwidth, the image processing device disclosed in Patent Document 1, for example, aims to improve effective bandwidth by including a cache memory for caching single slice data from a frame memory for storing frame data.
[Patent Document 1] Japanese Laid-Open Patent Application No. 2000-175201 Publication